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16 MULTIPLE CPU SYSTEM FUNCTION
16.4 Data Communication Between CPU Modules
Communication using CPU buffer memory and fixed scan communication area
This section describes the communication using CPU buffer memory and fixed scan communication area.
■Available area for communication
The following area can be used for communication.
■Instructions to be used for communication
Communication with each CPU module is enabled by issuing the following read/write instructions to each area.
• Write instruction: the instructions using the CPU buffer memory access device
*1
and the TO/DTO instruction
• Read instruction: the instructions using the CPU buffer memory access device
*1
and the FROM/DFROM instruction
*1 Specify "U3En\G" when accessing the CPU buffer memory and "U3En\HG" when accessing the fixed scan communication area.
■Data communication behavior
• When using an area within the CPU buffer memory
Data written to the area within the CPU buffer memory on the host CPU module using the write instruction can be read by
other CPU modules using the read instruction. Unlike the refresh, data registered during the instruction execution can be
directly read.
When data written to the CPU buffer memory on the CPU No.1 using the write instruction is read by CPU No.2 using the read
instruction:
Area Description
CPU buffer memory All the CPU buffer memory area except for the refresh area is available. The start address of the available area for each CPU
module varies depending on the refresh settings. The end address of the area is fixed by CPU module models.
Fixed scan communication
area
All the fixed scan communication area except for the refresh area is available. The start address of the available area for each
CPU module is HG0 and the end address varies depending on the refresh settings.
D0
D100
SM400
SM400
1
2
1
2
CPU No.1
CPU buffer memory
Data written using a write instruction
Refresh area
Write using a write instruction
Program
Execution of a write instruction
Read using
a read instruction
CPU No.2
Execution of a read instruction
CPU buffer memory
Refresh area
Program
Device
Device
Program
Program
U3E0\G1000
Send data
of CPU No.1
Send program
MOV U3E0\G1000 D100
Receive program
CPU No.1 (programmable controller CPU) CPU No.2 (programmable controller CPU)
MOV D0 U3E0\G1000
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