Mitsubishi Electric MELSEC iQ-R-R00CPU - Communication between CPU Modules in Error State

16 MULTIPLE CPU SYSTEM FUNCTION
16.4 Data Communication Between CPU Modules
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Communication between CPU modules in error state
The following section describes communication between CPU modules in an error state.
Behavior in receive data error state
A CPU module receiving illegal data due to noise and/or failure discards the received data. If a received data is discarded, the
receive-side CPU module keeps the last data received before discarding. When the CPU module receives the next correct
data, it updates the received data.
Refresh execution in an error state
The following table lists the refresh and send/receive operation between CPU modules when the host CPU module detects a
self diagnostic error. If one of the CPU modules enters into stop error state, the other CPU modules which are not in stop error
state keep data stored before the stop error occurs.
*1 This item indicates data transfer between user devices and the fixed scan communication area on the host CPU module.
*2 This item indicates data communication between the fixed scan communication areas on the host CPU module and other CPU modules.
*3 When an error occurs during normal operation, normal data generated immediately before the error occurs is continued to be sent
between the fixed scan communication areas on the host CPU module and other CPU modules.
*4 If the consistency check fails due to a parameter change in normal operation, refresh and data send/receive between the CPU modules
are continued.
Error Refresh
*1
Data communication
between CPU modules
*2
Minor error 
Moderate error Causes other than the following item 
Parameter error for fixed scan communication function (including the
consistency check during start-up)

*3*4

*3*4
Major error 
*3

*3