850
APPX
Appendix 5 List of Special Register Areas
SFC information
The following is the special register area relating to SFC information.
*1 There are restrictions on the firmware version of the supported CPU module and software version of the engineering tool. ( Page
1008 Added and Enhanced Functions)
System clock
The following is the list of special register areas relating to the system clock.
Fixed scan function information
The following is the list of special register areas relating to the fixed scan function information.
No. Name Data stored Details Set by
(setting
timing)
CPU
SD329 Online change (SFC
block) target block
number
SFC block number • A target SFC block number is stored while the online change (SFC
block) is being executed (SM329 = ON).
• FFFFH is stored when the online change (SFC block) is not executed.
S (Status
change)
Rn
*1
No. Name Data stored Details Set by
(setting
timing)
CPU
SD412 One second counter The number of counts
that is counted once
per second.
• The value in this register increments by one for each second
after the CPU module enters in RUN mode.
• A counting cycle from 0 to 65535 to 0 is repeated.
S (Status
change)
ALL
SD414 2n second clock
setting
Unit setting for 2n
second clock
• The n value of the 2n second clock is stored (Default: 30).
• Configurable range is -32768 to 32767 (0 to FFFFH).
UALL
SD415 2n ms clock setting Unit setting for 2n ms
clock
• The n value for the 2n ms clock is stored. (Default: 30).
• Configurable range is -32768 to 32767 (0 to FFFFH).
UALL
SD420 Scan counter The number of counts
that is counted once
for each scan.
• The value in this register increments by one for each scan after
the CPU module enters in RUN mode (however, the count is
skipped for scans by the initial execution type program).
• A counting cycle from 0 to 65535 to 0 is repeated.
S (Every END) ALL
No. Name Data stored Details Set by
(setting
timing)
CPU
SD480 Number of cycle
overrun events for
inter-module
synchronization cycle
program (I44)
0: No cycle overrun
event
1 to 65535:
Accumulated
number of cycle
overrun events
The number of events in which the inter-module synchronous
interrupt program (I44) has not been completed within the inter-
module synchronization cycle or the program cannot be executed
due to various reasons, such as execution of a higher-priority
interrupt program and interrupt disabling by the instruction
execution is stored. When the count exceeds 65535, it returns to 0
and starts a new cycle. The number of cycle overrun events is
counted regardless of the setting content for the error check setting
of the RAS setting (execution check of the inter-module
synchronous interrupt (I44)).
S (Status
change)
Rn
RnP
SD481 Number of cycle
overrun events for
multiple CPU
synchronization
program (I45)
0: No cycle overrun
event
1 to 65535:
Accumulated
number of cycle
overrun events
The number of events in which the multiple CPU synchronization
program (I45) has not been completed within the fixed scan
communication cycle or the program cannot be executed due to
various reasons, such as execution of a higher-priority interrupt
program and interrupt disabling by the instruction execution is
stored. When the count exceeds 65535, it returns to 0 and starts a
new cycle. The number of cycle overrun events is counted
regardless of the setting content for the error check setting of the
RAS setting (execution check of the multiple CPU synchronization
program (I45)).
S (Status
change)
Rn
*1
RnP
RnSF
SD484 Number of execution
section excess errors
for multiple CPU
synchronization
interrupt program
0: No error (Normal)
1 to 65535:
Accumulated
number of errors
The number of events in which the program is executed exceeding
the program execution section within the specified multiple CPU
synchronization cycle is stored. When the count exceeds 65535, it
returns to 0 and starts a new cycle. Note that the number of error
occurrences is counted regardless of the CPU module operation
setting for error detections within the RAS setting of the CPU
parameter.
S (Status
change)
Rn
*1
RnP
RnSF
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