Mitsubishi Electric MELSEC iQ-R-R00CPU - Page 315

16 MULTIPLE CPU SYSTEM FUNCTION
16.4 Data Communication Between CPU Modules
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16
Data guarantee for communication through direct access
The behavior varies depending on the area to be accessed.
■When accessing CPU buffer memory:
The program reads data in ascending order from the start address of the CPU buffer memory other than the refresh area, and
the write instruction writes send data in descending order from the end address of the CPU buffer memory other than the
refresh area. Therefore data inconsistency can be avoided by setting an interlock device at the start position of data to be
communicated.
Ex.
Interlock program in communication by direct access (when accessing CPU buffer memory)
• Program example
(1) CPU No.1 creates send data.
(2) CPU No.1 turns on the data setting complete bit.
[Data transfer with CPU No.2 END processing]
(3) CPU No.2 detects send data setting complete.
(4) CPU No.2 performs receive data processing.
(5) CPU No.2 turns on receive data processing complete.
[Data transfer with CPU No.1 END processing]
(6) CPU No.1 detects receive data processing complete, and turns off the data setting complete bit.
[Data transfer with CPU No.2 END processing]
(7) CPU No.2 detects that send data setting complete is turned off, and turns off receive data processing complete.
M0
RST G2048.0
SET G2048.0
RST M0
SET G2048.0
SET G2048.0
(1) (4)
(5)
(6) (7)
(2)
(3)
Write
instruction
Send program (CPU No.1)
Receive program (CPU No.2)
Set send data for user
setting areas
(U3E0\G2049 to
U3E0\G2057).
Operation using
receive data
(U3E0\G2049 to
U3E0\G2057)
U3E0\
G2048.0
U3E1\
G2048.0
U3E1\
G2048.0
U3E0\
G2048.0
U3E0\
U3E0\
U3E0\
G2048.0
U3E1\
G2048.0
U3E0\
G2048.0
U3E1\
G2048.0
U3E1\
U3E1\