23 MULTIPLE CPU SYSTEM FUNCTION
23.4 Data Communication Between CPU Modules
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23
■Avoidance of 64-bit data inconsistency
To avoid 64-bit data inconsistency, access the CPU buffer memory by specifying the start address as a multiple of four
similarly to the device to be specified.
(1) The CPU module assures a 64-bit data and write the data to the CPU buffer memory. (TO U3E0 K2052 D0 K4)
(2) The CPU module assures a 64-bit data and write the data to the CPU buffer memory. (TO U3E0 K2056 D4 K4)
(3) The CPU module assures a 64-bit data and read the data from the CPU buffer memory. (FROM U3E0 K2052 D100 K4)
(4) The CPU module assures a 64-bit data and read the data from the CPU buffer memory. (FROM U3E0 K2056 D104 K4)
D4
D0
G2048
G2052
G2056
D104
D100
(1)
(2)
(3)
(4)
Device
4 words (64 bits)
4 words (64 bits)
4 words (64 bits)
4 words (64 bits)
Device
CPU buffer memory
CPU No.1 CPU No.2
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