PA7
PA6
38 PA5
SN74LS04 (Typical)
37
PA4
36
PA3
35
PA2
PAl
PAO
TTL driving port A directly.
PC7
15
PC6
14
PC5
13
PC4
12
PC3
11
PC2·
PCl
PCO
CMOS and TTL driving port C directly.
SN74LS04
or MCl4069 •
(Typical)
PB7
PB6
PB5
29
PB4
28
PB3
27
PB2
PBl
PBO
CMOS or TTL driving port B directly.
PDO/ANO
PD1/ANl
22
PD2/AN2
21
PD3/AN3
20
VRL
19
VRH
18
PD6/1NT2
PD7
Port D
used
as
4-channel
AID
input with
bit 7 used
as
CMOS digital input.
MC6805R2, MC6805R3,
MC6805R3,
and MC68705R5
only.
Figure 8-2b. Typical Port Connections-Input Modes
The latched output data bit
(see
Figure
8-1)
must always
be
written. Therefore, any write to a port
writes
all
of
its data bits
even
though the port
DDR
is
set to input. This may
be
used
to initialize the
data register
and
avoid undefined outputs; however,
care
must
be
exercised when using
read-
modify-write instructions, since the data
read
corresponds to the pin
level
if the
DDR
is
an
input
(zero) and corresponds to the
latched output data when the
DDR
is
an
output (onel.
8.2
ANALOG-TO-DIGITAL CONVERTER
The MC6805R2, MC6805R3, MC68705R3 and MC68705R5 microcomputers have
an
8-bitanalog-to-
digital
(AI
D)
converter implemented
on
the chip using a successive approximation technique,
as
shown
in
Figure 8-3. Up
to
four external analog inputs,
via
port
0,
are
connected
to
the
AID
through a multiplexer. Four internal analog channels may
be
selected for calibration purposes
(VRH-VRL VRH-VRL/2, VRH-VRL/4, and
VRU· The accuracy of these internal channels will not
necessarily meet the accuracy specifications of the external channels.
The multiplexer selection
is
controlled
by
the
AID
control register (ACR) bits
0,
1,
and
2;
see
Table
8-1. This register
is
cleared during any reset condition. Refer
to
Figure 7-6 for the register configura-
tion.
8-3
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