PDQ/ANO
PD1/ANl
PD2/AN2
PD3/AN3
D/A
15
kO
(Typ)
Control
Logic
Count
1-of-8
Select
Multiplexer
AID
Result
I.-
.....
--.L_"--'---'-_"-
.....
--'
Register
Figure
8-3.
AI
D
Block
Diagram
Table
8-1.
AI
D
Input
MUX
Selection
AID
Control Register
Input Selected
AI
D Output (Hex)
ACR2
ACR1
ACRO
Min
Typ
Max
0
0 0
ANO
0
0
1 AN1
0
1 0 AN2
0
1 1 AN3
1
0 0
VRH*
FE
FF FF
1
0 1
VRL*
00
00
01
1
1
0
VRH/4*
3F
40
41
1
1 1
VRH/2*
7F
80
81
* Internal (Calibration) Levels
8
Whenever the
ACR
is
written, the conversion
in
progress
is
aborted, the conversion complete flag
(ACR bit
7)
is
cleared,
and
the selected input
is
sampled for five machine cycles and held internally.
During these five cycles, the analog input will appear approximately like a
25
picofarad (maximum)
capacitor
(plus approximately
10
pF
for packaging) charging through a 2.6 kilohm resistor (typical).
Refer to Figure
8-4.
The converter operates continuously using
30
machine cycles to complete a conversion
of
the
sampled analog input. When the conversion
is
complete, the digitized sample
of
digital value
is
placed
in
the
AID
result register (ARR), the conversion complete flag
is
set, the selected input
is
sampled again, and a new conversion
is
started.
TheA/D
is
ratiometric. Two reference voltages (VRH and VRU
are
supplied to the converter via
port D pins. An input
voltage equal
to
VRH
converts to
$FF
(full
scale)
and
an
input voltage equal
to
VRL converts to
$00.
An input voltage greater than
VRH
converts to
$FF
and no overflow indication
is
provided. Similarly,
an
input voltage
less
than VRL, but greater than VSS converts to
$00.
Max-
imum
and
minimum ratings must not
be
exceeded. For ratiometric conversion, the source
of
each
analog input should
use
VRH
as
the supply voltage and
be
referenced to VRL. To maintain the full
8-4
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