Nvidia Jetson AGX Xavier Series

Jetson AGX Xavier Series Product DG-09840-001_v2.5 | xv
Table 13-6. Jetson AGX Xavier SPI Pin Description ............................................................. 107
Table 13-7. SPI Interface Signal Routing Requirements ..................................................... 109
Table 13-8. SPI Signal Connections ...................................................................................... 109
Table 13-9. Recommended SPI Observation Test Points for Initial Boards ....................... 109
Table 13-10. Jetson AGX Xavier UART Pin Description.......................................................... 110
Table 13-11. UART Signal Connections .................................................................................. 111
Table 13-12. Reserved UART4_RX Routing Requirements ................................................... 112
Table 13-13. Jetson AGX Xavier CAN Pin Description ........................................................... 112
Table 13-14. CAN Interface Signal Routing Requirements ................................................... 113
Table 13-15. CAN Signal Connections .................................................................................... 113
Table 14-1. Jetson AGX Xavier Fan Pin Description ............................................................. 114
Table 14-2. Fan Signal Connections ..................................................................................... 115
Table 15-1. Jetson AGX Xavier JTAG Pin Description .......................................................... 118
Table 15-2. JTAG Signal Connections ................................................................................... 118
Table 15-3. Debug UART Connections .................................................................................. 119
Table 15-4. Strapping Pins .................................................................................................... 119
Table 15-5. Safety MCU Related Partial Pin Descriptions ................................................... 121
Table 16-1. MPIO Maximum Output Drive Current .............................................................. 124
Table 17-1. Unused MPIO Pins and Pin Groups ................................................................... 125