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APPENDIX C Example of CRC Calculation
Device address 06, read (03), starting register 0008, number of registers 0001
CRC Calculation
Function code Two byte (16 bit) Register Overflow
HB LB Bit
Load 16 bit register to all 1’s 1111 1111 1111 1111 0
First byte is address 06 0000 0110
Exclusive OR 1111 1111 1111 1001
1st shift 0111 1111 1111 1100 1
A001 1010 0000 0000 0001
Exclusive OR 1101 1111 1111 1101
2nd shift 0110 1111 1111 1110 1
A001 1010 0000 0000 0001
Exclusive OR 1100 1111 1111 1111
3rd shift 0110 0111 1111 1111 1
A001 1010 0000 0000 0001
Exclusive OR 1100 0111 1111 1110
4th shift 0110 0011 1111 1111 0
5th shift 0011 0001 1111 1111 1
A001 1010 0000 0000 0001
Exclusive OR 1001 0001 1111 1110
6th shift 0100 1000 1111 1111 0
7th shift 0010 0100 0111 1111 1
A001 1010 0000 0000 0001
Exclusive OR 1000 0100 0111 1110
8th shift 0100 0010 0011 1111 0
Second byte Read 03 0000 0011
Exclusive OR 0100 0010 0011 1100
1st shift 0010 0001 0001 1110 0
2nd shift 0001 0000 1000 1111 0
3rd shift 0000 1000 0100 0111 1
A001 1010 0000 0000 0001
Exclusive OR 1010 1000 0100 0110
4th shift 0101 0100 0010 0011 0
5th shift 0010 1010 0001 0001 1
A001 1010 0000 0000 0001
Exclusive OR 1000 1010 0001 0000
6th shift 0100 0101 0000 1000 0
7th shift 0010 0010 1000 0100 0
8th shift 0001 0001 0100 0010 0
Third byte Starting reg. 00 0000 0000
Exclusive OR 0001 0001 0100 0010
1st shift 0000 1000 1010 0001 0
2nd shift 0000 0100 0101 0000 1
A001 1010 0000 0000 0001
Exclusive OR 1010 0100 0101 0001
3rd shift 0101 0010 0010 1000 1
A001 1010 0000 0000 0001
Exclusive OR 1111 0010 0010 1001
4th shift 0111 1001 0001 0100 1