Omron CK3W-GC 00 Series - A-9-12 Gate3[I].Chan[3].Compb (TCR Output Status Register; A-9-13 Gate3[I].Chan[0].Status (Internal Memory Error Detection

Bit Name Function
29 CompClkSel Select an interpolation clock.
0: Servo clock
1: Phase clock
To change this setting, be sure to set CompareEnable to 0 beforehand. Also, make
sure that the interpolation clock period is 1 ms or less.
28
Reserve Always set 0.
27 to
26
CompOut-
Write
This is a 2-bit register
, which allows you to forcibly set a comparison output.
The lower bit is write enable, and the higher bit sets the status of a comparison output.
01: A comparison output is forcibly set to 0.
11: A comparison output is forcibly set to 1.
Writing 00 or 10 will reset the forced output.
25 CompOutPol Set the status of an OUT1 terminal output to a comparison output.
0: With comparison output = 1, OUT1 terminal = H (5 V output)
With comparison output = 0, OUT1 terminal = L (0 V output)
1: With comparison output = 1, OUT1 terminal = L (0 V output)
With comparison output = 0, OUT1 terminal = H (5 V output)
24 to
00
Reserve Always set 0.
A-9-12
Gate3[i].Chan[3].CompB (TCR Output Status Register)
Description TCR output status register
This register is valid for the CK3W-GC£200 Units only.
This register is read-only
. Writing is disabled.
Bit Name Function
31 CompOut Shows the OUT1 terminal status.
0: OUT1 terminal = L (0 V output)
1: OUT1 terminal = H (5 V output)
30 to
24
Reserve
23 to
12
TableWrite-
Pointer
Shows the buffer number to be written next on the comparison table.
When this data is n, buffers on the comparison table are empty from n to 4094.
When this data is
0, all buffers are empty.
When this data is 4095, all buffers are used and you can write no more comparison
values.
11 to 0 Compare-
Pointer
A buffer number on the comparison table with which the comparison is being executed
now.
When this data is
n, the comparison value of buffer n is valid.
When Compare Enable is 0, this data will be 0.
The comparison is done when ComparePointer is the same as TableWritePointer.
A-9-13
Gate3[i].Chan[0].Status (Internal Memory Error Detection)
Description Internal memory error detection
This register is read-only. Writing is disabled.
It can detect a memory error inside the Unit.
The errors are classified into the following two types.
Each error is removed by cycling the power supply
.
Appendices
A-40
CK3M-series Programmable Multi-Axis Controller User's Manual Hardware (O036)