Quectel EG25-G - Page 25

LTE Module Series
EG25-G Hardware Design
EG25-G_Hardware_Design 24 / 100
V
OL
max=0.38V
V
OH
min=2.01V
V
IL
min=-0.3V
V
IL
max=0.76V
V
IH
min=1.72V
V
IH
max=3.34V
SDC2_
DATA0
31
IO
SD card SDIO bus
DATA0
1.8V signaling:
V
OL
max=0.45V
V
OH
min=1.4V
V
IL
min=-0.3V
V
IL
max=0.58V
V
IH
min=1.27V
V
IH
max=2.0V
3.0V signaling:
V
OL
max=0.38V
V
OH
min=2.01V
V
IL
min=-0.3V
V
IL
max=0.76V
V
IH
min=1.72V
V
IH
max=3.34V
SDIO signal level can
be selected
according to SD card
supported level,
please refer to SD 3.0
protocol for more
details.
If unused, keep it
open.
SDC2_CLK
32
DO
SD card SDIO bus
clock
1.8V signaling:
V
OL
max=0.45V
V
OH
min=1.4V
3.0V signaling:
V
OL
max=0.38V
V
OH
min=2.01V
SDIO signal level can
be selected
according to SD card
supported level,
please refer to SD 3.0
protocol for more
details.
If unused, keep it
open.
SDC2_CMD
33
IO
SD card SDIO bus
command
1.8V signaling:
V
OL
max=0.45V
V
OH
min=1.4V
V
IL
min=-0.3V
V
IL
max=0.58V
V
IH
min=1.27V
V
IH
max=2.0V
3.0V signaling:
V
OL
max=0.38V
V
OH
min=2.01V
V
IL
min=-0.3V
V
IL
max=0.76V
V
IH
min=1.72V
SDIO signal level can
be selected
according to SD card
supported level,
please refer to SD 3.0
protocol for more
details.
If unused, keep it
open.