Quectel LTE-A Module Series - Page 28

LTE-A Module Series
EM120R-GL&EM160R-GL Hardware Design
EM120R-GL&EM160R-GL_Hardware_Design 27 / 79
The turn-on scenario is illustrated in the following figure.
VCC
FULL_CARD_POWER_OFF#
Booting
Active
Typical 11.6 s
OFF
RESET#
PCIE_RST_N
T1
T2
T3
T4
DPR/ANT_CONFIG
Figure 9: Turn-on Timing of the Module
Table 6: Description of Turn-on Timing of the Module
Index
Min.
Typical
Max.
Comment
T1
0 ms
50 ms
-
RESET# is pulled up internally, and it would be
de-asserted 50 ms after VCC is powered on.
T2
0 ms
20 ms
-
FULL_CARD_POWER_OFF# could be de-asserted
before or after RESET#, 20 ms is a recommended value
when it is controlled by GPIO.
T3
0 ms
15 ms
20 ms
DPR or ANT_CONFIG should be asserted before
modem initialize.
T4
-
100 ms
-
PCIE_RST_N should be de-asserted 100 ms after
FULL_CARD_POWER_OFF#.