Quectel LTE-A Module Series - Page 32

LTE-A Module Series
EM120R-GL&EM160R-GL Hardware Design
EM120R-GL&EM160R-GL_Hardware_Design 31 / 79
Host Module
RESET_N
Reset
Logic
GPIO
67
VDD 1.8 V
Reset pulse
200–700 ms
R1
100K
R5
100K
R4
10Ω
Q2
NMOS
Figure 14: Reference Circuit of RESET_N with NMOS Driving Circuit
Module
RESET_N
Reset
Logic
67
VDD 1.8 V
200–700 ms
S1
TVS
R1
100K
33 pF
C1
Note: The capacitor C1 is recommended to be less than 47 pF.
Figure 15: Reference Circuit of RESET_N with Button