Quectel RG520N-AT - Page 44

5G Module Series
RG520N-AT_Hardware_Design 43 / 109
Table 10: Pin Definition of RESET_N
The recommended circuit is the same as the PWRKEY control circuit. An open-drain/open-collector driver
or button can be used to control the RESET_N.
RESET_N
≥ 500 ms
MCU
GPIO
Module
Reset pulse
4.7K
47K
Q1
Figure 15: Reference Circuit of RESET_N with Driving Circuit
RESET_N
Module
S2
Close to S2
TVS
1K
Reset pulse
R1
Figure 16: Reference Circuit of RESET_N with a Button
Pin Name
Pin No.
I/O
Description
Comment
RESET_N
8
DI
Resets the module
Internally pulled up to 1.8 V
with a 40 kΩ resistor.