Quectel RG520N-AT - I2 S Interface

5G Module Series
RG520N-AT_Hardware_Design 51 / 109
Table 16: Pin Definition of I2C Interface
4.5. I2S Interface*
The module provides one I2S interface.
Pin definition is listed as follows:
Table 17: Pin Definition of I2S Interface
The following figure shows a reference design of I2S interface with an external codec IC.
Pin Name
Pin No.
I/O
Description
Comment
I2C_SCL
77
OD
I2C serial clock
Pull them up to VDD_EXT
with an external 4.7 kΩ
resistor respectively. If
unused, keep them open.
I2C_SDA
78
OD
I2C serial data
Pin Name
Pin No.
I/O
Description
Comment
I2S_WS
259
DIO
I2S word select
In master mode, it is an
output signal.
In slave mode, it is an
input signal.
I2S_SCK
256
DIO
I2S clock
In master mode, it is an
output signal.
In slave mode, it is an
input signal.
I2S_DIN
257
DI
I2S data in
I2S_DOUT
255
DO
I2S data out
MCLK
79
DO
Master clock output for
codec
If unused, keep it open.