Quectel RG520N-AT - Page 54

5G Module Series
RG520N-AT_Hardware_Design 53 / 109
The module supports 16-bit linear data format. The following figures show the primary mode’s timing
relationship with 8 kHz PCM_SYNC and 2048 kHz PCM_CLK, as well as the auxiliary mode’s timing
relationship with 8 kHz PCM_SYNC and 256 kHz PCM_CLK.
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
MSB
125 μs
1 2 256255
PCM_DIN
MSB
LSBMSB
Figure 23: Primary Mode Timing
PCM_CLK
PCM_SYNC
PCM_DOUT
MSB
LSB
PCM_DIN
125 μs
MSB
1 2 3231
LSB
Figure 24: Auxiliary Mode Timing
Clock and mode can be configured via AT+QDAI, and the default configuration is master mode using
short frame sync format with 2048 kHz PCM_CLK and 8 kHz PCM_SYNC. See document [3] about
AT+QDAI for details.