Quectel RG520N-AT - Page 64

5G Module Series
RG520N-AT_Hardware_Design 63 / 109
The following figure illustrates the PCIe interface connection.
PCIE_TX0_M
PCIE_TX0_P
PCIE_RST_N
PCIE_RX0_P
Module
PCIE_REFCLK_M
PCIE_REFCLK_P
PCIE_WAKE_N
PCIE_CLKREQ_N
PCIE_RX0_M
PCIE_CLKREQ_N
PCIE_WAKE_N
PCIE_RST_N
PCIE_REFCLK_P
PCIE_REFCLK_M
PCIE_RX_M
PCIE_RX_P
PCIE_TX_P
PCIE_TX_M
R1
4.7K
R2
4.7K
VDD_EXT
C1
220 nF
C2
220 nF
C3
220 nF
C4
220 nF
R3
NM_10K
R4 0R
R5 0R
PCIe
Device
Figure 32: PCIe Interface Connection
PCIE_RX0_P
34
AI
PCIe receive 0 (+)
PCIE_RX1_M
35
AI
PCIe receive 1 (-)
PCIE_RX1_P
37
AI
PCIe receive 1 (+)
PCIE_CLKREQ_N
36
OD
PCIe clock request
1.8 V power domain.
In root complex mode, it is
an input signal.
In endpoint mode, it is an
output signal.
PCIE_RST_N
39
DIO
PCIe reset
1.8 V power domain.
In root complex mode, it is
an output signal.
In endpoint mode, it is an
input signal.
PCIE_WAKE_N
30
OD
PCIe wake up
1.8 V power domain.
In root complex mode, it is
an input signal.
In endpoint mode, it is an
output signal.