RIGOL
© 2008 RIGOL Technologies, Inc.
User‟s Guide for Logic Signal Output Module
NOTE
When setting SCLK, SDA, CS and TFS, selected D0~D15 cannot be double
set. For example, SCLK has set to be D0; SDA cannot be assigned to D0,
unless SCLK being set to another line.
SPI, IIC, PO protocols provide both analog and digital channel voltage
output. Users can configure them individually.
When analog voltage is higher than 4.2V, digital voltage will automatically
adjust to be 3/8 of analog voltage.
Set digital channels voltage. The
default is 3.3V.
User-defined mode (1.4V~4.2V)
Turn off digital voltage output.