SICK HIPERFACE DSL - Page 153

Path in ZIP archive File
dslm_n_bus dslm_n_spi
Resource
\External_Blocks bus_ctrl.vhd
spi_ctrl.vhd
x
x
Open source interface blocks
If a Xilinx ISE project is loaded, the NGC net list must be copied directly into the project
folder.
NOTE
Please note that the NGC net lists cannot be added via the menu commands "Project >
Add Source" or "Project > Add Copy of Source".
The instantiation of the NGC net list is by a "black_box" in the source code of the top
level design.
In VHDL, this instantiation is in accordance with the following template:
component dslm_n
port (...);
endcomponent;
...
attribute box_type : string;
attribute box_type of dslm_n: component is „black_box“;
...
begin
...
<component_name> : dslm_n
port map (...);
...
In Verilog, this instantiation is in accordance with the following template:
module dslm_n (...);
endmodule
...
dslm_n <module_name> (...);
//synthesis attribute box_typeofdslm_n is„black_box“
...
9.6.3 Demo project
To get started quickly, each IP Core is supplied with a demo project for Xilinx ISE. This
demo project contains all the settings to begin the installation of the IP Core with the
accompanying top level design ("wrapper").
Prerequisites for the demo project are:
•
All the files from the ZIP archive for the IP Core have been extracted into a folder.
Any preferred location may be used for this.
•
All the tools listed have been installed on the development computer.
FPGA IP-CORE 9
8017595/ZTW6/2018-01-15 | SICK T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
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Subject to change without notice