SICK HIPERFACE DSL - 1 List of Figures

1 List of figures
1. Drive system with HIPERFACE DSL
®
............................................................................ 7
2. Length of protocol packages......................................................................................10
3. Data channels in HIPERFACE DSL
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........................................................................... 11
4. HIPERFACE DSL
®
SensorHub interface.....................................................................14
5. Interface circuit with separate encoder cable.......................................................... 16
6. Interface circuit with two core cable (integrated in cable).......................................16
7. Block diagrams of the "standard" DSL Master IP Core with interfaces.................. 19
8. Reset procedure......................................................................................................... 20
9. DSL system interfaces................................................................................................22
10. SPI-PIPE interface time control.................................................................................. 24
11. "Read Pipeline" transaction....................................................................................... 24
12. Sample signal............................................................................................................. 26
13. Register block overview..............................................................................................29
14. Interrupt masking....................................................................................................... 39
15. DSL Slave status and summary.................................................................................46
16. Sequence of the bytes to calculate the CRC.............................................................48
17. Status table for DSL system start..............................................................................59
18. Position value format..................................................................................................62
19. Polling of position registers in free running mode....................................................64
20. Polling of rotation speed registers in free running mode.........................................64
21. SYNC mode signals.....................................................................................................66
22. Polling registers for the fast position in SYNC mode................................................ 66
23. Polling of rotation speed registers in SYNC mode.................................................... 66
24. Polling the safe position.............................................................................................67
25. Reading from remote register.................................................................................... 68
26. "Long message" characteristics.................................................................................69
27. Example of a "long message" read command.......................................................... 72
28. Reset of the Parameters Channel............................................................................. 73
29. Acknowledgment of event bits...................................................................................74
30. Tree structure of the resources database.................................................................87
31. Code disc position....................................................................................................114
32. Workflows for data storage......................................................................................126
33. sHub
®
categories......................................................................................................133
34. Block circuit diagram of the DSL Master IP Core................................................... 136
35. Combination examples of interface blocks ........................................................... 140
36. Serial interface block signals ................................................................................. 140
37. Time control of the SPI.............................................................................................142
38. Parallel interface block signals............................................................................... 145
39. Allocation of parallel interface block to host..........................................................147
40. Read access basic interface................................................................................... 149
41. Write access basic interface....................................................................................149
42. Connection of the hybrid motor cable to the servo controller ..............................163
43. Pin layout M23..........................................................................................................167
LIST OF FIGURES 1
8017595/ZTW6/2018-01-15 | SICK T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
5
Subject to change without notice