at this area needs to consider RF requirements for the actual components selec‐
tion and PCB layout.
•
DSL signal transmission is done with about 10 MHz frequency but square signal
harmonics can reach frequencies beyond (to 60 MHz) which should be considered
for layout design.
•
The used motor cable shall meet the impedance requirements of (110 +/-10)
Ohm to avoid signal reflections.
•
DSL line connection to the servo controller shall be separated from the motor
power connection point.
•
A good main shielding connection to a low inductance path shall allow draining
motor power residual current. For the DSL-line shielding a separate connection
point is recommended. For the connection unshielded DSL lines shall be avoided
or kept as short as possible (<20 mm).
4.2 FPGA IP Core
The frequency inverter system communicates with the DSL motor feedback system via
a special protocol logic circuit that is designated as the DSL Master. The circuit is sup‐
plied by SICK and must be installed in an FPGA component. It is supplied as an Intellec‐
tual Property Core (IP Core). The DSL Master IP Core is supplied in different forms,
depending on the FPGA vendor preferred by the user (compiled netlist or encrypted
VHDL). If there is sufficient space in the FPGA being used, the DSL Master can be
installed in the same component as the frequency inverter application.
CAUTION
There are two different IP Cores available, one for standard and one for safety applica‐
tions. This manual only describes the standard variant. Please choose according to the
desired system.
For interfacing the IP Core, several options are available. For details of those interface
blocks see chapter 9.1.
The following figure show the possible combinations of IP Core and interface block vari‐
ants.
4 HARDWARE INSTALLATION
18
T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
8017595/ZTW6/2018-01-15 | SICK
Subject to change without notice
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