12 Glossary
8B/10B 8 bit/10 bit code (line code for transmission of 8 bits with data in 10 bit lengths to
achieve DC balance)
CRC Cyclic Redundancy Check (algorithm to determine data checksum) DSL Digital Servo
Link, complete name: HIPERFACE DSL
®
DSL Digital Servo Link
EDIF
Electronic Design Interchange Format (format for electronic exchange of FPGA netlists)
FIFO First in – First out (storage method in which the first stored elements are the first to be
discarded)
FPGA Field Programmable Gate Array (programmable digital logic component)
IP Core
Intellectual Property Core, for integration into ICs or chip provided for FPGAs
Long Message Protocol component for polling parameter data of an encoder that must first be
processed by the encoder.
Motor feedback sys‐
tem
Rotary or linear encoder for use in servo drives
RS485 Radio Sector Standard 485 (also designated as EIA-485 or TIA- 485-A standard for ser‐
ial data transmission over symmetric pair cables)
RSSI Received Signal Strength Indicator
SensorHub
Interface between a motor feedback system and an external sensor component in a
drive system
Short Message Protocol component for polling directly transmitted parameter data of an encoder
SPI
Serial Peripheral Interface (serial bus system for digital switching)
VHDL Very high speed integrated circuit Hardware Description Language (hardware abstrac‐
tion language for FPGAs)
12
GLOSSARY
170
T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
8017595/ZTW6/2018-01-15 | SICK
Subject to change without notice
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