If the bit is set, the frequency inverter application can trigger a "short message". Pro‐
vided no answer has been received from the DSL Slave, this bit remains deleted. As the
processing duration of a "long message" in the motor feedback system is not specified,
a time limit condition is installed in the DSL Master. If the time limit is exceeded,
attempts are made again automatically (see under RET bit).
6.3.5 Event mask
In the event mask registers MASK_H/MASK_L, the events are set with which the inter-
rupt signal is set.
Several events can be masked to trigger an interrupt. In addition, events from the DSL
Slave summary can be combined with these events (see chapter 6.3.6). This is
explained in figure 14 .
OR
Events (DSL Master)
Reg
04h
Reg
05h
--
PRST
DTE
POS
SCE
--
VPOS
SUM
--
FRES
FREL
--
MIN
ANS
QMLW
--
Status (DSL Slave)
Reg
18h
SUM7
SUM0
SUM1
SUM3
SUM5
SUM4
SUM2
SUM6
INT output
OR
Event Mask
Reg
06h
Reg
07h
--
MPRST
MDTE
MPOS
MSCE
--
MVPOS
MSUM
--
MFRES
MFREL
--
MMIN
MANS
MQMLW
--
Status Mask
Reg
08h
MSUM7
MSUM0
MSUM1
MSUM3
MSUM5
MSUM4
MSUM2
MSUM6
Figure 14: Interrupt masking
NOTE
It should be noted that the SUM bit is an OR connection of all bits of the status bit is an
OR connection of all bits of the status summary (SUMMARY register).
Register 06h:
High Byte event mask
X-0 W-0 X-0 X-0 W-0 X-0 W-0 W-0
MSUM MPOS MDTE MPRST
Bit 7 Bit 0
Bit 7 Not implemented: Read as "0".
Bit 6
MSUM: Mask for remote event monitoring
1 = DSL Slave events that are masked in the SUMMARY register set the interrupt sig‐
nal.
0 = DSL Slave events that are masked in the SUMMARY register do not set the inter-
rupt signal.
REGISTER MAP
6
8017595/ZTW6/2018-01-15 | SICK T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
39
Subject to change without notice
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