NOTE
Each transaction via SPI is included in spi_sel by a "1" level. With each spi_sel
reset, a new transaction is started. This causes the online-status to be retransmitted in
the first two bytes.
The time sequence is shown in the following time sequence diagram and in table 189.
spi_sel
spi_clk
spi_mosi
spi_miso
POL=0
PHA=1
1 2 3 4 5 6 7 8 1 2 3
1 2 3 4 5 6 7 8 1 2
a
b c
d e
n
n
f
g
3
h
i
Figure 37: Time control of the SPI
The time control is given in the table below:
Table 189: Time control of the SPI
Diagram
position
Description Minimum Maximum Units
a Setting spi_sel before spi_clk 25 ns
b Time for spi_clk high 50 ns
c Time for spi_clk low 50 ns
d Setting spi_mosi before spi_clk
low
10 ns
e Keep spi_mosi at spi_clk low 25 ns
f Keep spi_sel at spi_clk low 260 ns
g Delay spi_miso at spi_clk high 25 60 ns
h Delay spi_miso at spi_sel low 25 60 ns
i Time for spi_sel low 50 ns
9.2.2 Dummy read process
Due to the transmission of the online-status, Online Status read transactions need less
time for transmission via spi_mosi than when receiving via spi_miso. Therefore,
when receiving via spi_miso, dummy read transactions must be inserted into
spi_mosi to avoid unwanted extra transactions.
A read access to register 3Fh has no effect and must be used for this purpose.
9.2.3 Read individual register
Using the SPI transaction "Read individual register", an individual register can be read
in the IP Core of the DSL Master.
Symbol Meaning
R Access bit: Read ("1")
REG ADDR Register address (00h to 7Fh)
DUMMY ADDR Register address for the dummy read process (3Fh)
ONLINE STATUS H Online-status – High byte
ONLINE STATUS L Online-status – Low byte
REG DATA Register content
9 FPGA IP-CORE
142
T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
8017595/ZTW6/2018-01-15 | SICK
Subject to change without notice
To Next Page
Loading...
