spi_ss
spi_clk
spi_mosi
spi_miso
R REG ADDR
ONLINE STATUS H ONLINE STATUS L REG DATA
R DUMMY ADDR R DUMMY ADDR
9.2.4 Read several registers
Using the SPI transaction "Read several registers", several registers can be read in the
IP Core of the DSL Master. Registers can be selected for reading in any sequence
desired.
Symbol Meaning
R Access bit: Read ("1")
REG ADDR x Register address (00h to 7Fh), no. x
DUMMY ADDR Register address for the dummy read process (3Fh)
ONLINE STATUS H Online-status – High byte
ONLINE STATUS L Online-status – Low byte
REG DATA x Content of register x
spi_ss
spi_clk
spi_mosi
spi_miso
R REG ADDR 1
ONLINE STATUS H ONLINE STATUS L REG DATA 1
R REG ADDR 2
REG DATA 2
R
DUMMY ADDR R DUMMY ADDR
9.2.5 Write to individual register
Using the SPI transaction "Write to individual register", an individual register can be writ‐
ten to in the IP Core of the DSL Master.
Symbol Meaning
W Access bit: Write ("0")
REG ADDR Register address (00h to 7Fh)
REG DATA Register content
ONLINE STATUS H Online-status – High byte
ONLINE STATUS L Online-status – Low byte
spi_ss
spi_clk
spi_mosi
spi_miso
W REG ADDR
ONLINE STATUS H ONLINE STATUS L
REG DATA
9.2.6 Write to several registers (automatic increment)
Using the SPI transaction "Write to several registers", several registers can be written to
in the IP Core of the DSL Master. During the transaction only the address of the starting
register is transmitted. With each register data byte, the IP Core raises the addresses
automatically.
FPGA IP-CORE 9
8017595/ZTW6/2018-01-15 | SICK T E C H N I C A L I N F O R M A T I O N | HIPERFACE DSL
®
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Subject to change without notice
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