Siemens Argus 7SR22 - Check Synchronising Mode; Figure 4.9.4-1 Check Sync Function

7SR210 & 7SR220 Description of Operation
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4.9.4 Check Synchronising Mode
The Man Override Sync input is provided to bypass the voltage and synchronising checks to provide an
emergency close function. Similarly, check synchronising can be overridden by the 79 Override Sync input
during autoreclose. Override can be set by binary inputs, Control commands and the function keys.
For the relay to issue a Check Sync Close the following conditions have to be met: -
The Line and Bus voltages must both be considered live.
25 Check Sync Angle – the phase difference between the line and bus voltages has to be less than the phase
angle setting value. Whilst within the limits the phase angle can be increasing or decreasing and the element will
still issue a valid close signal.
25 Check Sync Slip, [if enabled] – the frequency difference between line and bus has to be less than the slip
frequency setting value.
25 Check Sync Timer, [if enabled] – the phase angle and voltage blocking features have to be within their
parameters for the length of the slip timer setting. If either the phase angle or the voltage elements fall outside of
their limits the slip timer is reset. If they subsequently come back in then the slip timer has to time out before an
output is given. (This ensures that a close output will not be given if there is a transient disturbance on the system
due to e.g. some remote switching operations).
25 Line Undervolts, [if enabled] – the line voltage has to be above the line under-voltage setting value and also
above 5V for an output to be given.
25 Bus Undervolts, [if enabled] – the bus voltage has to be above the bus under-voltage setting value and also
above 5V for an output to be given.
25 Volt Differential, [if enabled] – the difference between the line and bus voltages has to be less than the
differential voltage detector setting value for an output to be given.
The synchronising is always started in the Check Synchronising mode of operation and the Check Synchronising
limits are applied. To proceed to System Synchronisation a system split must be detected as described in section
4.9.5
Phase Within Range ?
SLIP
Line U/V
Block
Bus U/V
BLock
V Block
D
Phase Angle Setting
&
Slip Frequency Setting
Block
Block
Block
CheckSync
Close
&
Slip Timer
Setting
Slip Timer
F
Angle
Slip Within Range ?
Figure 4.9.4-1 Check Sync Function