Siemens ST750 - Page 25

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Page
25 of 73
Version 008
Status
Released
Last Editor Nathan Fearnhead
Date
16/06/2017
Document Name Configuration Control
Document No.
667/CC/32750/000
Copyright © Mobility 2017. All Rights Reserved. Mobility is a division of Siemens Plc
As introduced in paragraph 3.2.5 (CPU PCB) communications between CPU PCB and Intelligent
Detector Backplanes are carried out via fast serial link, over Cat5/RJ45 cable. With reference to
Figure 19, the fast serial link is connected from PL2 on the PHS processor daughter board to the
Serial IN socket on the first Intelligent Detector Backplane. Please note, an Input Output
Expansion Kit can be specified, which also utilises the Fast Serial Link. For information on the
Input Output Expansion Kit please refer to paragraph 3.8. The serial link is connected from the
first Intelligent Detector Backplane OUT socket into the second Intelligent Detector Backplane IN
socket.
With reference to Figure 20, -24 DC power is provided to the Intelligent Detector Backplanes
from the Detector Power Terminal Blocks, on the Backplane Rack Assembly. Orange wire will be
used for the positive connection and Grey for negative connection. Additional power can be
provided for Intelligent Detector Backplanes, refer to paragraph 3.16.
Loop activation signals are passed to the Intelligent Detector Backplanes from the Loop
Termination PCB via PL8. Refer to paragraph 3.12 for information on Loop Termination PCB’s.
Figure 19
Figure 20
Power for
Intelligent
Detector
Backplanes
Detector
Power IN
Detector
Power OUT
to next
Intelligent
Detector
Backplane
Connection
from Loop
Termination
PCB PL8
Fast
Serial Link
from I/O
card
Fast
Serial Link
to next
Intelligent
Detector
Backplane
Serial I/O
Address
Switch