SONIX SN8P2624 - Table of Contents

SN8P2624
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 3 Version 0.3
Table of Content
AMENDENT HISTORY................................................................................................................................ 2
1
1
1
PRODUCT OVERVIEW......................................................................................................................... 7
1.1 FEATURES........................................................................................................................................ 7
1.2 SYSTEM BLOCK DIAGRAM.......................................................................................................... 8
1.3 PIN ASSIGNMENT........................................................................................................................... 9
1.4 PIN DESCRIPTIONS....................................................................................................................... 10
1.5 PIN CIRCUIT DIAGRAMS............................................................................................................. 11
2
2
2
CENTRAL PROCESSOR UNIT (CPU) .............................................................................................. 12
2.1 MEMORY MAP............................................................................................................................... 12
2.1.1 PROGRAM MEMORY (ROM) ................................................................................................. 12
2.1.1.1 RESET VECTOR (0000H) .................................................................................................. 13
2.1.1.2 INTERRUPT VECTOR (0008H)......................................................................................... 14
2.1.1.3 LOOK-UP TABLE DESCRIPTION.................................................................................... 16
2.1.1.4 JUMP TABLE DESCRIPTION........................................................................................... 18
2.1.1.5 CHECKSUM CALCULATION........................................................................................... 20
2.1.2 CODE OPTION TABLE........................................................................................................... 21
2.1.3 DATA MEMORY (RAM)........................................................................................................... 22
2.1.4 SYSTEM REGISTER.................................................................................................................23
2.1.4.1 SYSTEM REGISTER TABLE ............................................................................................ 23
2.1.4.2 SYSTEM REGISTER DESCRIPTION ............................................................................... 23
2.1.4.3 BIT DEFINITION of SYSTEM REGISTER....................................................................... 24
2.1.4.4 ACCUMULATOR ............................................................................................................... 25
2.1.4.5 PROGRAM FLAG............................................................................................................... 26
2.1.4.6 PROGRAM COUNTER....................................................................................................... 27
2.1.4.7 H, L REGISTERS................................................................................................................. 30
2.1.4.8 Y, Z REGISTERS................................................................................................................. 31
2.1.4.9 R REGISTERS..................................................................................................................... 32
2.2 ADDRESSING MODE .................................................................................................................... 33
2.2.1 IMMEDIATE ADDRESSING MODE....................................................................................... 33
2.2.2 DIRECTLY ADDRESSING MODE .......................................................................................... 33
2.2.3 INDIRECTLY ADDRESSING MODE ...................................................................................... 33
2.3 STACK OPERATION...................................................................................................................... 34
2.3.1 OVERVIEW .............................................................................................................................. 34
2.3.2 STACK REGISTERS.................................................................................................................35
2.3.3 STACK OPERATION EXAMPLE............................................................................................. 36