SONIX SN8P2624 - 6.9 TC1 Interrupt Operation

SN8P2624
8-Bit Micro-Controller
SONiX TECHNOLOGY CO., LTD Page 65 Version 0.3
6.9 TC1 INTERRUPT OPERATION
When the TC1C counter overflows, the TC1IRQ will be set to “1” no matter the TC1IEN is enable or disable. If the
TC1IEN and the trigger event TC1IRQ is set to be “1”. As the result, the system will execute the interrupt vector. If the
TC1IEN = 0, the trigger event TC1IRQ is still set to be “1”. Moreover, the system won’t execute interrupt vector even
when the TC1IEN is set to be “1”. Users need to be cautious with the operation under multi-interrupt situation.
¾ Example: TC1 interrupt request setup.
B0BCLR FTC1IEN ; Disable TC1 interrupt service
B0BCLR FTC1ENB ; Disable TC1 timer
MOV A, #20H ;
B0MOV TC1M, A ; Set TC1 clock = Fcpu / 64
MOV A, #74H ; Set TC1C initial value = 74H
B0MOV TC1C, A ; Set TC1 interval = 10 ms
B0BSET FTC1IEN ; Enable TC1 interrupt service
B0BCLR FTC1IRQ ; Clear TC1 interrupt request flag
B0BSET FTC1ENB ; Enable TC1 timer
B0BSET FGIE ; Enable GIE
¾ Example: TC1 interrupt service routine.
ORG 8 ; Interrupt vector
JMP INT_SERVICE
INT_SERVICE:
… ; Push routine to save ACC and PFLAG to buffers.
B0BTS1 FTC1IRQ ; Check TC1IRQ
JMP EXIT_INT ; TC1IRQ = 0, exit interrupt vector
B0BCLR FTC1IRQ ; Reset TC1IRQ
MOV A, #74H
B0MOV TC1C, A ; Reset TC1C.
… ; TC1 interrupt service routine
…
EXIT_INT:
… ; Pop routine to load ACC and PFLAG from buffers.
RETI ; Exit interrupt vector