DocID027559 Rev 5 17/54
AN4661 Power supplies
53
2. The two 2.2 µF ceramic capacitors should be replaced by two 100 nF decoupling capacitors when the
voltage regulator is OFF.
3. The 4.7 µF ceramic capacitor must be connected to one of the V
DD
pin.
4. V
DDA
=V
DD
and V
SSA
=V
SS
.
1.3 Reset & power supply supervisor
1.3.1 Power-on reset (POR)/power-down reset (PDR)
The device has an integrated POR/PDR circuitry that allows a proper operation starting from
1.8 V.
The device remains in reset mode when V
DD
/V
DDA
is below a specified threshold,
VPOR/PDR, without the need for an external reset circuit. For more details concerning the
power on/power-down reset threshold, refer to the electrical characteristics of the
datasheet.
Figure 9. Power on reset/power down reset waveform
1. tRSTTEMPO is approximately 2.6 ms. VPOR/PDR rising edge is 1.74 V (typ.) and VPOR/PDR falling edge
is 1.70 V (typ.). Refer to the product datasheets for the actual value.
On the packages embedding the PDR_ON pin, the power supply supervisor is enabled by
holding PDR_ON high. On the other packages, the power supply supervisor is always
enabled.
1.3.2 Programmable voltage detector (PVD)
The PVD can be used to monitor the V
DD
power supply by comparing it to a threshold
selected by the PLS[2:0] bits in the PWR power control register (PWR_CR1).
The PVD is enabled by setting the PVDE bit.
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