DocID027559 Rev 5 47/54
AN4661 Recommended PCB routing guidelines for STM32F7 Series devices
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• Avoid using a serpentine routing for the clock signal and as less via(s) as possible for
the whole path. a via alters the impedance and adds a reflection to the signal.
8.4.4 Embedded trace macrocell (ETM)
Interface connectivity
The ETM enables the reconstruction of the program execution. The data are traced using
the data watchpoint and trace (DWT) component or the instruction trace macrocell (ITM)
whereas instructions are traced using the embedded trace macrocell (ETM). The ETM
interface is synchronous with the data bus of 4 lines D[0:3] and the clock signal CLK.
Interface signals layout guidelines
• Reference the plane using GND or PWR (if PWR, add 10nf stitching cap between PWR
and GND
• Trace the impedance: 50Ω ± 10%
• All the data trace should be as short as possible (<=25 mm),
• Trace the lines which should run on the same layer with a solid ground plane
underneath it without a via.
• Trace the clock which should have only point-to-point connection. Any stubs should be
avoided.
• It is strongly recommended also for other (data) lines to be point-to-point only. If any
stubs are needed, they should be as short as possible. If longer are required, there
should be a possibility to optionally disconnect them (e.g. by jumpers).
8.5 Package layout recommendation
8.5.1 BGA 216 0.8 mm pitch design example
With 0.8 mm pitch BGA balls, fan-out vias are needed to route the balls to other layers on
the PCB. Through-vias are used in this example, which cost less than blind, buried vias. For
four adjacent BGA land pads, it is possible to have only one via as showing in
Figure 28 and
Figure 29. The traces are routed of two first row and two first colon without fan-out via. The
current pitch size allows to route only one trace between two adjacent BGA land pads.
Figure 30 shows an example of ideal SDRAM signals fan-out vias with power and gnd
signals. These signals can be optimized to achieve the routing and length matching in an
another layer before connecting to an SDRAM IC.
Table 9. BGA 216 0.8 mm pitch package information
Package information (mm) Design parameters (mm)
Ball pitch : 0.8 Via size : hole size ∅= 0.2, pad size: 0.45, plane clearance: 0.65
Ball size : 0.4 Trace width : 0.10/0.125
Number of rows/columns : 15x15 Trace/trace space : 0.10/0.125
Package solder Pad: SMD BGA land size (Ball pad): ∅= 0.4, solder mask: 0.5
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