Reference design AN4661
36/54 DocID027559 Rev 5
7 Reference design
7.1 Description
The reference design shown in Figure 24, is based on the STM32F756NGH6, a highly
integrated microcontroller running at 216 MHz, that combines the Cortex
®
-M7 32-bit RISC
CPU core with 1 Mbyte of embedded Flash memory and system SRAM up to 320 Kbytes
(including Data TCM RAM 64 Kbytes), 16 Kbytes of instruction RAM (ITCM-RAM) and 4
Kbytes of backup SRAM.
7.1.1 Clocks
Two clock sources are used for the microcontroller:
• LSE: X2– 32.768 kHz crystal for the embedded RTC.
• HSE: X1– 25 MHz crystal.
Refer to Section 3: Clocks on page 24.
7.1.2 Reset
The reset signal of STM32F74xxx/STM32F75xxx devices is low active and the reset
sources include:
• Reset button B1
• Debugging Tools from JTAG/SWD connector CN15 and ETM trace connector CN12
Refer to Section 1.3: Reset & power supply supervisor on page 17.
7.1.3 Boot mode
The STM32F74xxx/STM32F75xxx devices can boot from any region from 0x0000 0000 to
0x2004 FFFF.
The boot space is configured by setting BOOT pin and the boot base address programmed
in the BOOT_ADD0 and BOOT_ADD1 option bytes.
For more details refer to Section 4: Boot configuration on page 27.
Note: In the Low-power mode (more specially in Standby mode), the boot mode is mandatory to
be able to connect to tools (the device should boot from the SRAM).
7.1.4 SWJ interface
Refer to Section 5: Debug management on page 29.
7.1.5 Power supply
Refer to Section 1: Power supplies on page 7.
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