RM0440 Rev 4 1197/2126
RM0440 Advanced-control timers (TIM1/TIM8/TIM20)
1226
Bits 16, 6:4 OC3M[3:0]: Output compare 3 mode
These bits define the behavior of the output reference signal tim_oc3ref from which tim_oc3
and tim_oc3n are derived. tim_oc3ref is active high whereas tim_oc3 and tim_oc3n active
level depends on CC3P and CC3NP bits.
0000: Frozen - The comparison between the output compare register TIMx_CCR3 and the
counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a
timing base).
0001: Set channel 3 to active level on match. tim_oc3ref signal is forced high when the
counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3).
0010: Set channel 3 to inactive level on match. tim_oc3ref signal is forced low when the
counter TIMx_CNT matches the capture/compare register 3 (TIMx_CCR3).
0011: Toggle - tim_oc3ref toggles when TIMx_CNT=TIMx_CCR3.
0100: Force inactive level - tim_oc3ref is forced low.
0101: Force active level - tim_oc3ref is forced high.
0110: PWM mode 1 - In upcounting, channel 3 is active as long as TIMx_CNT<TIMx_CCR3
else inactive. In downcounting, channel 3 is inactive (tim_oc3ref=‘0’) as long as
TIMx_CNT>TIMx_CCR3 else active (tim_oc3ref=’1’).
0111: PWM mode 2 - In upcounting, channel 3 is inactive as long as
TIMx_CNT<TIMx_CCR3 else active. In downcounting, channel 3 is active as long as
TIMx_CNT>TIMx_CCR3 else inactive.
1000: Retrigerrable
OPM mode 1 - In up-counting mode, the channel is active until a trigger
event is detected (on tim_trgi signal). Then, a comparison is performed as in PWM
mode 1 and the channels becomes active again at the next update. In down-counting
mode, the channel is inactive until a trigger event is detected (on tim_trgi signal).
Then, a comparison is performed as in PWM mode 1 and the channels becomes
inactive again at the next update.
1001: Retrigerrable
OPM mode 2 - In up-counting mode, the channel is inactive until a
trigger event is detected (on tim_trgi signal). Then, a comparison is performed as in
PWM mode 2 and the channels becomes inactive again at the next update. In down-
counting mode, the channel is active until a trigger event is detected (on tim_trgi
signal). Then, a comparison is performed as in PWM mode 1 and the channels
becomes active again at the next update.
1010: Pulse on compare: a pulse is generated on tim_oc3ref upon CCR3 match event, as
per PWPRSC[2:0] and PW[7:0] bitfields programming in TIMxECR.
1011: Direction output. The tim_oc3ref signal is overridden by a copy of the DIR bit.
1100: Combined PWM mode 1 - tim_oc3ref has the same behavior as in PWM mode 1.
tim_oc3refc is the logical OR between tim_oc3ref and tim_oc4ref.
1101: Combined PWM mode 2 - tim_oc3ref has the same behavior as in PWM mode 2.
tim_oc3refc is the logical AND between tim_oc3ref and tim_oc4ref.
1110: Asymmetric PWM mode 1 - tim_oc3ref has the same behavior as in PWM mode 1.
tim_oc3refc outputs tim_oc3ref when the counter is counting up, tim_oc4ref when it is
counting down.
1111: Asymmetric PWM mode 2 - tim_oc3ref has the same behavior as in PWM mode 2.
tim_oc3refc outputs tim_oc3ref when the counter is counting up, tim_oc4ref when it is
counting down.
Note: These bits can not be modified as long as LOCK level 3 has been programmed (LOCK
bits in TIMx_BDTR register) and CC1S=’00’ (the channel is configured in output).
Note: In PWM mode, the OCREF level changes only when the result of the comparison
changes or when the output compare mode switches from “frozen” mode to “PWM”
mode.
On channels having a complementary output, this bit field is preloaded. If the CCPC bit is set in
the TIMx_CR2 register then the OC3M active bits take the new value from the preloaded bits
only when a COM event is generated.
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