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SPRS717H –OCTOBER 2011–REVISED MAY 2015
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Table 4-1. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET BUFFER PULLUP
ZCE BALL ZCZ BALL TYPE BALL RESET RESET REL. ZCE POWER / HYS
PIN NAME [2] SIGNAL NAME [3] MODE [4] REL. STATE STRENGTH /DOWN TYPE I/O CELL [13]
NUMBER [1] NUMBER [1] [5] STATE [6] MODE [8] ZCZ POWER [9] [10]
[7] (mA) [11] [12]
A1, A19, D10, A1, A18 , F8, VSS VSS NA GND
E7, E8, E9, G8, G9, G11,
E10, F6, F7, G12, H6, H7,
F8, F12, F13, H8, H9, H10,
G8, G12, H9, H12, J6, J7,
H10, H11, J5, J8, J9, J10,
J6, J9, J11, J11, K7, K9,
J14, J15, K8, K10, K11,
K9, K11, K12, L10, L11, L12,
L5, L6, L9, L13, M6, M7,
L11, L14, L15, M8, M9, M10 ,
M9, M10, M12, N7,
M11, N8, N10, N11, V1,
N12, P7, P8, V18
P12, P13,
P14, R10,
T10, W1, W19
D8 E8 VSSA_ADC VSSA_ADC NA GND
P16 M14, N14 VSSA_USB VSSA_USB NA GND
V11 V11 VSS_OSC VSS_OSC
(28)
NA A
NA A5 VSS_RTC VSS_RTC
(29)
NA A
A16 A10 WARMRSTn nRESETIN_OUT 0 I/OD 0
(25)
0(PU)
(11)
0 VDDSHV6 / Yes 4 PU/PD LVCMOS
(8)
VDDSHV6
C15 A15 XDMA_EVENT_INTR0 xdma_event_intr0 0 I Z
(4) (9)
VDDSHV6 / Yes 4 PU/PD LVCMOS
VDDSHV6
timer4 2 I/O
clkout1 3 O
spi1_cs1 4 I/O
pr1_pru1_pru_r31_16 5 I
EMU2 6 I/O
gpio0_19 7 I/O
B15 D14 XDMA_EVENT_INTR1 xdma_event_intr1 0 I Z L 7 VDDSHV6 / Yes 4 PU/PD LVCMOS
VDDSHV6
tclkin 2 I
clkout2 3 O
timer7 4 I/O
pr1_pru0_pru_r31_16 5 I
EMU3 6 I/O
gpio0_20 7 I/O
W11 V10 XTALIN OSC0_IN 0 I Z Z 0 VDDS_OSC / Yes NA PD
(2)
LVCMOS
VDDS_OSC
W12 U11 XTALOUT OSC0_OUT 0 O
(24) (24)
0 VDDS_OSC / NA NA
(15)
NA LVCMOS
VDDS_OSC
48 Terminal Configuration and Functions Copyright © 2011–2015, Texas Instruments Incorporated
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