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SPRS717H –OCTOBER 2011–REVISED MAY 2015
Table 4-1. Pin Attributes (ZCE and ZCZ Packages) (continued)
BALL RESET BUFFER PULLUP
ZCE BALL ZCZ BALL TYPE BALL RESET RESET REL. ZCE POWER / HYS
PIN NAME [2] SIGNAL NAME [3] MODE [4] REL. STATE STRENGTH /DOWN TYPE I/O CELL [13]
NUMBER [1] NUMBER [1] [5] STATE [6] MODE [8] ZCZ POWER [9] [10]
[7] (mA) [11] [12]
D7 D8 VDDA_ADC VDDA_ADC NA PWR
D12, F16, E6, E14, F9, VDDS VDDS NA PWR
M16, T6, T14 K13, N6, P9,
P14
R8, R9, R11, P7, P8 VDDSHV1 VDDSHV1 NA PWR
R12, R13
NA P10, P11 VDDSHV2 VDDSHV2 NA PWR
NA P12, P13 VDDSHV3 VDDSHV3 NA PWR
G15, H14, H14, J14 VDDSHV4 VDDSHV4 NA PWR
H15
M14, M15, K14, L14 VDDSHV5 VDDSHV5 NA PWR
N15
E11, E12, E10, E11, VDDSHV6 VDDSHV6 NA PWR
E13, F14, P6, E12, E13,
R7 F14, G14, N5,
P5, P6
G5, H5, H6, E5, F5, G5, VDDS_DDR VDDS_DDR NA PWR
K4, K5, M5, H5, J5, K5, L5
M6, N5
U10 R11 VDDS_OSC VDDS_OSC NA PWR
T8 R10 VDDS_PLL_CORE_LCD VDDS_PLL_CORE_LCD NA PWR
C5 E7 VDDS_PLL_DDR VDDS_PLL_DDR NA PWR
H16 H15 VDDS_PLL_MPU VDDS_PLL_MPU NA PWR
C6 D7 VDDS_RTC VDDS_RTC NA PWR
C10 E9 VDDS_SRAM_CORE_BG VDDS_SRAM_CORE_BG NA PWR
C12 D10 VDDS_SRAM_MPU_BB VDDS_SRAM_MPU_BB NA PWR
F9, F11, G9, F6, F7, G6, VDD_CORE VDD_CORE NA PWR
G11, H7, H8, G7, G10,
H12, H13, J7, H11, J12, K6,
J8, J12, J13, K8, K12, L6,
K15, K16, L7, L7, L8, L9,
L8, L12, L13, M11, M13 ,
M7, M8, M12, N8, N9, N12,
M13, N9, N13
N11, P9, P11
NA F10, F11, VDD_MPU VDD_MPU
(30)
NA PWR
F12, F13,
G13, H13,
J13
NA A2 VDD_MPU_MON VDD_MPU_MON
(31)
NA A
R5 M5 VPP VPP NA PWR
B9 A9 VREFN VREFN 0 AP Z Z 0 VDDA_ADC / NA NA NA Analog
VDDA_ADC
A9 B9 VREFP VREFP 0 AP Z Z 0 VDDA_ADC / NA NA NA Analog
VDDA_ADC
Copyright © 2011–2015, Texas Instruments Incorporated Terminal Configuration and Functions 47
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