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General| Frequency Range | 2400 - 2483.5 MHz |
|---|---|
| Interface | SPI |
| Operating Temperature | -40 to +85 °C |
| Modulation Types | 2-FSK, GFSK, OOK |
| Supply Voltage | 1.8 V to 3.6 V |
| Package | QFN-20 |
| Data Rate | 1.2 kbps to 500 kbps |
Core radio performance metrics, including sensitivity and output power.
Describes analog capabilities like modulation formats and frequency synthesis.
Details digital aspects such as packet handling and SPI interface.
Highlights power consumption in sleep modes and fast startup times.
Details current draw in various operating modes and states.
Specifies performance metrics for the RF receiver.
Details performance metrics for the RF transmitter.
Describes crystal frequency, tolerance, and ESR parameters.
Details characteristics of the low-power RC oscillator.
Specifies synthesizer performance like phase noise and settling time.
Provides characteristics of the on-chip analog temperature sensor.
Defines DC voltage levels for digital inputs/outputs.
Outlines requirements for proper power-on reset functionality.
Explains the status byte for MCU communication via SPI.
Describes how to access configuration and status registers via SPI.
Details the procedure for reading register fields via SPI.
Lists command strobes for controlling radio states and operations.
Explains access methods for TX and RX FIFOs via SPI.
Details access to the PATABLE for PA power settings.
Describes the four-pin SPI interface for MCU communication.
Explains usage of GDO pins for status and control signals.
Details the three-pin control feature for radio states.
Explains frequency offset compensation for 2-FSK, GFSK, MSK.
Describes the bit synchronization algorithm for clock recovery.
Explains byte synchronization using sync word search.
Explains data whitening for improved over-the-air data characteristics.
Details the structure of data packets, including preamble and sync word.
Describes address, length, and CRC filtering in receive mode.
Explains the CRC check implementations and status reporting.
Details packet preparation and transmission logic.
Describes packet reception, sync word detection, and status appending.
Discusses firmware-level handling of packet reception/transmission.
Details 2-FSK and GFSK modulation, including shaping.
Explains MSK modulation and phase shift characteristics.
Describes OOK modulation as simple on-off keying.
Explains sync word detection modes and carrier sense integration.
Details PQT for qualifying sync word detection.
Describes RSSI measurement for signal level estimation.
Explains carrier sense functionality for channel assessment.
Details CCA for indicating channel availability.
Describes LQI as a metric for received signal quality.
Details FEC implementation for reducing bit error rate.
Describes matrix interleaving for handling burst errors.
Details automatic and manual reset procedures.
Explains crystal oscillator control and management.
Describes control of the voltage regulator for different states.
Details receive and transmit modes and calibration options.
Explains WOR functionality for periodic wake-ups.
Covers timing aspects of state transitions and operations.
Details the optional timer for automatic RX termination.
Details self-calibration for VCO and PLL for reliable operation.
Explains alternative operation using an external reference signal.
Explains asynchronous data transfer mode and its limitations.
Describes synchronous serial data transfer and packet handling.
Summarizes regulations for 2.4 GHz band usage.
Discusses FHSS and multi-channel system benefits.
Covers wideband modulation compliance with FCC part 15.247.
Explains using burst transmissions to reduce active mode time.
Details continuous transmission capabilities at high data rates.
Explains compensating for frequency offset and drift.
Describes GFSK for improved spectral efficiency.
Discusses design considerations for low-cost systems.
Provides guidance for low-power battery-operated applications.
Explains methods for extending link range by increasing output power.
Lists registers retaining values during SLEEP mode.
Lists registers that reset upon entering SLEEP mode.
Describes status registers providing information on device state.
Illustrates recommended PCB layout for the QFN 20 package.
Recommends lead-free reflow soldering procedures.
Details revisions and changes made to the document.
