Texas Instruments CC2500 - Page 62

CC2500
S
WRS040
C
Page
62
of
89
0x03: FIFOTHR
–
RX FIFO and TX FIFO T
hresholds
Bit
Field Name
Reset
R/W
Description
7:4
Reserved
0
R0
Write 0 fo
r compatibility with possible future extensions
3:0
FIFO_THR[3:0]
7 (0111)
R/W
Set the threshold for the TX FIFO and RX FIFO. The threshold
is exceeded when the number of bytes in the FIFO is equal to
or higher than the threshold value.
Setting
Bytes in T
X FIFO
Bytes in RX FIFO
0 (0000)
61
4
1 (0001)
57
8
2 (0010)
53
12
3 (0011)
49
16
4 (0100)
45
20
5 (0101)
41
24
6 (0110)
37
28
7 (0111)
33
32
8 (1000)
29
36
9 (1001)
25
40
10 (1010)
21
44
11 (1011)
17
48
12 (1100)
13
52
13 (1101)
9
56
14 (11
10)
5
60
15 (1111)
1
64
0x04: SYNC1
–
Sync Word, High Byte
Bit
Field Name
Reset
R/W
Description
7:0
SYNC[15:8]
211 (0xD3)
R/W
8 MSB of 16
-
bit sync word
0x05: SYNC0
–
Sync Word, Low Byte
Bit
Field Name
Reset
R/W
Description
7:0
SYNC[7:0]
145 (0x91)
R/W
8 LSB of 16
-
bit sync word
0x06: PKTLEN
–
Packet Length
Bit
Field Name
Reset
R/W
Description
7:0
PACKET_LENGTH
255 (0xFF)
R/W
Indicates the packet length when fixed
packet length is
enabled. If variable length packets are used, this value
indicates
the maximum length packets allowed.