VTI Instruments EX1000A - Configure the TRIG Event System

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EX10xxA Programming 109
The ARM delay is configured with the vtex10xxA_set_arm_delay function, specified with a value
in seconds from 0 to 4294 with a resolution of 0.000001 (1 µs). The ARM delay is the time between
the recognition of the ARM event and the transition into the TRIG layer of the trigger model.
Example: This code block sets an ARM delay of 5 ms.
vtex10xxA_set_arm_delay(vi, 0.005);
The current ARM delay is queried with the vtex10xxA_get_arm_delay query.
Configure the TRIG event system
The TRIG source is configured with the vtex10xxA_set_trigger_sourceEx function. The TRIG
event can be specified to be any combination of LXI Trigger Bus channel transitions or levels,
Digital I/O channel transitions or levels, LXI LAN event transitions or levels and Timer ticks, or
simply be set to Immediate. If multiple sources for a TRIG event are specified, they are logically
combined as follows:
TRIG event = [(Timer tick event) AND (LXI alarm event) AND (LAN event) AND (Digital I/O event) AND (Trigger
Bus event)]
Within each digital hardware port, it is also possible to select multiple channels and multiple
conditions for a specific channel. In that case, they are logically combined as follows:
Digital I/O event = (Ch 7 events) AND (Ch 6 events) … AND (Ch 0 events)
Finally, within each channel, the four event conditions of Positive Edge, Negative Edge, Positive
Level, and Negative Level are OR’ed together.
As an example, if a Digital I/O event is specified to be a combination of a Pos. Level on channel 3,
a Pos. Edge on channel 6, and a Neg. Edge on channel 6, the event will be satisfied when a Pos.
Level on channel 3 occurs simultaneously with a Positive Edge or a Negative Edge transition on
channel 6. While the Digital I/O event structure was used as an example, the Trigger Bus event
structure operates in the same manner.
This function accepts the following parameters:
 an array of four 8-bit values representing the enabling of events from any of the 8 channels of
the trigger bus. The order of the values is: positive edge, negative edge, positive level,
negative level. Each value is specified in either decimal (0 through 255) or hex (0x00 through
0xFF). Within the 8-bit field, the MSB corresponds to LXI Trigger Bus (VTB) channel 7 and
the LSB corresponds to LXI Trigger Bus (VTB) channel 0.
 an array of four 8-bit values representing the enabling of events from any of the 8 channels of
the digital I/O port. The order of the values is: positive edge, negative edge, positive level,
negative level. Each value is specified in either decimal (0 through 255) or hex (0x00 through
0xFF). Within the 8-bit field, the MSB corresponds to DIO channel 7 and the LSB
corresponds to DIO channel 0.
 an array of four 8-bit values representing the enabling of events from any of the eight LAN
events. The order of the values is: positive edge, negative edge, positive level, negative level.
Each value is specified in either decimal (0 through 255) or hex (0x00 through 0xFF). Within
the 8-bit field, the MSB corresponds to LAN 7 and the LSB corresponds to LAN 0.
 a Boolean value indicating the enable status of the Timer event
 a Boolean value indicating the enable status of the Immediate event.
 a Boolean value indicating the enable status of the LXI alarm event
Regardless of this setting, software triggers are always enabled.