Xilinx MultiLINX Series User Manual

Hardware User Guide
4-8 Xilinx Development System
-- Can use attributes to assign pin locations in
-
-- Foundation VHDL
attribute pinnum of Dout:signal is
"p13,14,16,18,19,20,21,22";
end jcounter;
architecture jcounter_arch of jcounter is
begin
if CLK’ event and CLK=’1’ then--CLK rising edge
Dout (7 downto 1) <= Dout (6 downto 0);--shift -
Dout (7 downto 1) <= Dout (6 downto 0);--shift -
Dout (0) <= not Dout (7);--Last bit inverted --
-- back into first bit
end if;
end process;
end jcounter_arch;

Xilinx MultiLINX Series Specifications

General

Brand	Xilinx
Model	MultiLINX Series
Category	Cables and connectors
Language	English