Xilinx MultiLINX Series User Manual

Hardware User Guide
2-18 Xilinx Development System
Figure 2-10 SelectMAP Mode (Virtex with Asynchronous
Probing)
JTAG Mode (XC9000, Virtex, Spartan, XC5200,
XC4000)
The following figure shows in detail the JTAG Mode connections for
XC9000, Virtex, Spartan, XC5200, and XC4000 devices.
D0
D1
D2
D3
D4
D5
D6
D7
RDY/BUSY
CS2
CS1
CS0 (CS)
WS
GND
CCLK
DIN
RT
TDI
TCK
TMS
RST
TRIG
RD (TDO)
PWR
Vcco
RS (RDWR)
CLK2-IN
CLK2-OUT
CLK1-IN
CLK1-OUT
DONE (D / P)
PROG
INIT
4
2
3
1
NOTE: Pull-up resistors are 4.7k ohm.
Circuit Board
XILINX device
MultiLINX Connectors
VCCVCC Vcco
Vcco
(optional)
System Clock (x)
System Clock (y)
(optional)
M0 M1 M2
CCLK
CS
DONE
PROGRAM
INIT
D7 D6 D5 D3 D4 D2 D1 D0
WRITE
BUSY/DOUT
GCK (x)
GCK (y)
User Logic
flip-flops & latches,
LUTRAMS,
& block RAMS
Capture Control
Logic
CAPTURE
CAPCLK
User I/O: RESET
User I/O: TRIGGER User I/O
(optional)
X8935

Xilinx MultiLINX Series Specifications

General

Brand	Xilinx
Model	MultiLINX Series
Category	Cables and connectors
Language	English