FPGA Design Demonstration Board
Hardware User Guide 3-9
Seven-Segment Displays (U6, U7, U8)
Three seven-segment displays are included with the leftmost display
(U6) connect to the XC3020A FPGA. The rightmost two displays (U7
and U8) connect to the XC4003E device.
Each LED segment is turned on by driving the corresponding FPGA
pin ‘LOW’ with a logic ‘0.’ The decimal point on U8 connects to the
INIT pin of the XC4003E (pin 41) and serves as a programming error
indicator. The decimal point should be on while the FPGA is in its
internal clearing state, then it should remain off during configuration.
If the decimal point comes back on, a programming error has
occurred.
The decimal points on U6 and U7 are tied to the Low During Config-
uration (LDC) pins of the XC3020A and XC4003E, respectively. The
decimal points are on while the FPGAs wait to be configured.
The following table shows the I/O pin definitions. The following
figure shows the seven-segment display of the FPGA demonstration
board.
Table 3-3 Seven-Segment I/O Connections
Display Segment XC3020A XC4003E XC4003E
U6 U7 U8
a383949
b393848
c403647
d563546
e492945
f534050
g554451
decimal point 30 37 41
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