Hardware User Guide
3-32 Xilinx Development System
7. Connect XChecker to J1 (for the XC3020A) and J2 (for the
XC4003E) on the FPGA Demonstration Board.
8. Set the mode switches.
When you use the XChecker Cable, the M0, M1, and M2 switches
must be on. This setting causes the device to be in the serial slave
mode. Refer to the Table 3-14 for the switch settings necessary to
configure a daisy chain.
9. Power up the target system.
10. Start your software package.
For information on starting the Hardware Debugger software, see
the“Starting Hardware Debugger” section.
Loading with a Configuration PROM
If you already have a design programmed in a PROM, skip to step 5.
You can also view or edit the demonstration designs supplied with
the Xilinx software tools.
Note Make backups before making changes to any demonstration
design files.
1. Place and route the design.
Produce a routed design, design_name using a design entry tool
and the appropriate place and route tool.
2. Generate a configuration bitstream for the design,
design_name.bit with the appropriate configuration options
using the BitGen program.
3. Create a PROM file.
Generate a PROM file (design_name) using the PROMGen
program. See the PROMGen documentation in the Development
System Reference Guide to create a PROM file.
Note The XC1700 series of configuration serial PROMs must be
programmed with the reset polarity set for active-Low.
4. Place the PROM on the FPGA Demonstration Board.
After you have a PROM that has a configuration bitstream
programmed into it, place it into the FPGA Demonstration Board
To Next Page
Loading...
Need help?
General