• I2C address 0x6A
PCIe Clock
[Figure 3, callout 41]
The VCK190 board includes an IDT 85411 (U39) 1:2 clock buer for the PCIe clock fan out to
the Versal ACAP. The 100 MHz PCIE_CLK_P/N clock from the PCIe 8-lane edge connector (P3)
drives the U39 clock input.
The U39's buered outputs are used to create dierenal clock pairs to the ACAP U1 GTY103/
GTY104 PCIe interface:
• U39's Q0 PCIE_CLK0_P/N are connected to PCIE_TX/RX[0:3] interface GTY103
GTY_REFCLK0 pins W39 (P) and W40 (N), which are A/C coupled
• U39's Q1 PCIE_CLK1_P/N are connected to PCIE_TX/RX[4:7] interface GTY104
GTY_REFCLK0 pins R39 (P) and R40 (N), which are A/C coupled
• 1:2 clock buer
○ Q0: 100 MHz LVDS
○ Q1: 100 MHz LVDS
Programmable FMCP MGT SI570 Clock with Buffer
[Figure 3, callout 45]
The VCK190 board has an I2C programmable SI570 low-jier 3.3V LVDS dierenal oscillator
(U205) driving SI53340 (U206) 2-to-4 clock buer input CLK0. The clock buer generates four
copies of the input clock. The SI53340 CLK1 second input is driven by 8A34001 (U219) output
Q2. The SI53340 input clock select is controlled by 2-pin header J306 with default jumper o,
selecng the CLK0 SI570 input. At power-up, SI570 (U205) defaults to an output frequency of
100.000 MHz. User applicaons or the System Controller can change the output frequency
within the range of 10 MHz to 945 MHz through the I2C bus interface. Power cycling the
VCK190 board reverts this user clock to the default frequency of 100.000 MHz.
• Programmable oscillator: Silicon Labs SI570BAB000299DG (10 MHz-945 MHz range,
100.000 MHz default)
• I2C address 0x5F
• LVDS dierenal output, total stability: 61.5 ppm
The four SI53340 (U206) outputs are connected as follows:
• Outputs
○ Q0: SI570_8A34001_MUX_BUF0_P/N capacitor coupled to GTY201
FMCP1_DP[0:3]_C2M/M2C interface GTY_REFCLK0 pins AB11 (P) and AB10 (N)
Chapter 3: Board Component Descriptions
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 49
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