Xilinx VCK190 Series User Manual

A PS Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet interface (see the
gure in PMC MIO[49] and LPD_MIO[12:25]: GEM1 Ethernet), which connects to TI
DP83867IRPAP U198 Ethernet RGMII PHY before being routed to a vercal dual-stacked RJ45
Ethernet connector J307 (upper receptacle). The RGMII Ethernet PHY is boot strapped to PHY
address (0x01) and Auto Negoaon is set to Enable.
PMC MIO[49] and LPD_MIO[12:25]: GEM1 Ethernet
[Figure 3, callout 17]
A PS Gigabit Ethernet MAC (GEM) implements a 10/100/1000 Mb/s Ethernet interface (see the
following gure), which connects to TI DP83867IRPAP U134 Ethernet RGMII PHY before being
routed to a vercal dual-stacked RJ45 Ethernet connector J307 (lower receptacle). The RGMII
Ethernet PHY is boot strapped to PHY address (0x02) and Auto Negoaon is set to Enable.
The following gure shows the dual Ethernet topology.
Figure 16: Dual RGMII Ethernet
XCVC1902
ACAP
RGMII
LPD MIO[0:11 24:25] LPD MIO[12:23 24:25]
GEM0 U198
DP83867IR
10/100/1000
PHY
MDIO
RGMII
GEM1 U134
DP83867IR
10/100/1000
PHY
MDIO
MII
J307
Upper
RJ45
J307
Lower
RJ45
25 MHz
Crystal
MII
25 MHz
Crystal
X23203-100119
Ethernet PHY (Three Resets)
[Figure 3, callout 35]
Each DP83867ISRGZ PHY (GEM0 U198, GEM1 U134) is reset by its GEMx_RESET_B generated
by dedicated pushbuon switches and PMC_MIO signals as shown in the following gure. The
POR_B signal generated by the TPS389001DSER U10 POR device (acvated by pushbuon
SW2) is wired in parallel to each Ethernet PHY reset circuit.
Chapter 3: Board Component Descriptions
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 42
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Xilinx VCK190 Series Specifications

General

Brand	Xilinx
Model	VCK190 Series
Category	Motherboard
Language	English