VADJ_FMC Power Rail
The VCK190 evaluaon board implements the ANSI/VITA 57.4 IPMI support funconality. The
power control of the VADJ_FMC power rail is managed by the ZU4 U125 System Controller. This
rail powers both FMCP HSPC J51 and J53 VADJ pins, as well as the XCVC1902 U1 VCCO on the
FMCP interface banks 706, 707, and 708. The valid values of the VADJ_FMC rail are 0, 1.2V, or
1.5V. At power on, the System Controller detects if an FMC module is installed on J51 or J53.
The following sequence of acons then take place:
• If no card is aached to a FMCP connector, the VADJ_FMC voltage is set to 1.5V
• When an FMC card is aached, its IIC EEPROM is read to nd a VADJ voltage supported by
both the VCK190 board and the FMC module, within the available choices of 0, 1.2V, or 1.5V
• If no valid informaon is found in an aached FMC card IIC EEPROM, the VADJ_FMC rail is
set to 0.0V
The System Controller user interface allows the FMC IPMI roune to be overridden and an
explicit value can be set for the VADJ_FMC rail. The override mode is useful for FMC mezzanine
cards that do not contain valid IPMI EPROM data dened by the ANSI/VITA 57.4 specicaon.
User I/O
[Figure 3, callout 22 and 23]
The VCK190 board provides these GPIO bank 306 user and general purpose I/O capabilies:
• Four user LEDs (callout 22)
○ GPIO_LED[0:3]: DS6, DS5, DS4, DS3
• 4-posion user DIP switch (callout 23)
○ GPIO_DIP_SW[0:3]: SW6
• Two user pushbuons and CPU reset switch (callouts 24 and 25)
○ GPIO_PB[0:1]: SW4, SW5
The detailed ACAP connecons for the feature described in this secon are documented in the
VCK190 board XDC le, referenced in Appendix B: Xilinx Design Constraints.
Power and Status LEDs
[Figure 3, callout 29]
The following table denes the power and status LEDs. For user-controlled GPIO LED details,
see User I/O.
Chapter 3: Board Component Descriptions
UG1366 (v1.0) January 7, 2021 www.xilinx.com
VCK190 Board User Guide 60
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