Xilinx Virtex-4 - Page 11

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 11
UG074 (v2.2) February 22, 2010
R
Interfacing to an FPGA Fabric-Based Statistics Block . . . . . . . . . . . . . . . . . . . . . . . 161
When the Ethernet MAC Is Implemented with the Host Bus . . . . . . . . . . . . . . . . . . . 161
When the Ethernet MAC Is Implemented with the DCR Bus . . . . . . . . . . . . . . . . . . . 163
Chapter 7: Using the Embedded Ethernet MAC
Accessing the Ethernet MAC from the CORE Generator tool . . . . . . . . . . . . . . . . 167
Simulating the Ethernet MAC using the Ethernet MAC wrappers . . . . . . . . . . . 167
Appendix A: Ethernet MAC Timing Model
Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Input Setup/Hold Times Relative to Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Clock to Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Core Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Timing Diagram and Timing Parameter Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
www.BDTIC.com/XILINX