Xilinx Virtex-4 - Tri-Mode Operation with Byte PHY Enabled (Full-Duplex Only)

110 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 4: Physical Interface
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Tri-Mode Operation with Byte PHY Enabled (Full-Duplex Only)
Figure 4-10 shows an alternative clock management scheme for the tri-mode GMII
interface operating in full-duplex mode. In this scheme, the EMAC is configured to run in
1 Gb/s mode at all times, resulting in the datapath being 8 bits wide at both the client and
the physical interfaces at all speeds. At 1 Gb/s all external logic is clocked at 125 MHz. At
100 Mb/s and 10 Mb/s, the logic is clocked at 12.5 MHz and 1.25 MHz, respectively.
Figure 4-9: GMII Tri-Mode Operation Clock Management
CLIENTEMAC#TXGMIIMIICLKIN
PHYEMAC#GTXCLK
CLIENTEMAC#TXCLIENTCLKIN
EMAC#CLIENTTXCLIENTCLKOUT
CLIENTEMAC#RXCLIENTCLKIN
EMAC#CLIENTRXCLIENTCLKOUT
CLIENTEMAC#DCMLOCKED
EMAC#PHYTXD[7:0]
EMAC#
BUFG
BUFGMUX
GTX_CLK
TX CLIENT
LOGIC
BUFG
RX CLIENT
LOGIC
OBUF
GMII_TXD_#[7:0]
Q
Q
D
MII_TX_CLK_#
SPEED_IS_10_100
PHYEMAC#MIITXCLK
UG074_3_55_021010
OBUF
ODDR
GMII_TX_CLK_#
D1
CLKIN
CLKFB
DCM
CLK0
D2
0
1
0
1
PHYEMAC#RXCLK
PHYEMAC#RXD[7:0]
GMII_RXD_#[7:0]
SPEED_IS_10_100
IBUF
QD
GMII_RX_CLK_#
IBUFG
0
1
BUFGMUX
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