Xilinx Virtex-4 - Clock Signals

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 25
UG074 (v2.2) February 22, 2010
Ethernet MAC Signal Descriptions
R
Clock Signals
Table 2-4 shows the clock signals necessary to drive the Ethernet MAC.
Table 2-4: Clock Signals
Signal Direction Description
PHYEMAC#GTXCLK Input
Clock supplied by the user to derive the other transmit clocks.
Clock tolerance must be within the IEEE Std 802.3-2002
specification.
EMAC#CLIENTRXCLIENTCLKOUT Output
Clock for receive client generated by the clock generator of the
Ethernet MAC.
EMAC#CLIENTTXCLIENTCLKOUT Output
Clock for transmit client generated by the clock generator of the
Ethernet MAC.
CLIENTEMAC#RXCLIENTCLKIN Input
Clock from receive client for the running of the receiver engine of
the Ethernet MAC.
(1)
CLIENTEMAC#TXCLIENTCLKIN Input
Clock from transmit client for the running of the transmitter
engine of the Ethernet MAC.
(1)
EMAC#CLIENTTXGMIIMIICLKOUT Output
Clock for MII, GMII, and RGMII modules. Generated by the clock
generator of the Ethernet MAC.
CLIENTEMAC#TXGMIIMIICLKIN Input
Clock from MII, GMII, and RGMII modules for the running of the
MII/GMII/RGMII transmitter layer of the Ethernet MAC.
(1)
Notes:
1. The Ethernet MAC uses this clock to generate an internal clock that eliminates clock skew between the Ethernet MAC and the client
logic in the FPGA.
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