Xilinx Virtex-4 - Features

16 www.xilinx.com Embedded Tri-Mode Ethernet MAC User Guide
UG074 (v2.2) February 22, 2010
Chapter 1: Introduction
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Features
The key features of the Virtex-4 FPGA Ethernet MAC are:
• Fully integrated 10/100/1000 Mb/s Ethernet MAC
• Designed to the IEEE Std 802.3-2002 specification
• Configurable full-duplex operation in 10/100/1000 Mb/s
• Configurable half-duplex operation in 10/100 Mb/s
• Management Data Input/Output (MDIO) interface to manage objects in the physical
layer
• User-accessible raw statistic vector outputs
• Support for VLAN frames
• Configurable inter-frame gap (IFG) adjustment in full-duplex operation
• Configurable in-band Frame Check Sequence (FCS) field passing on both transmit
and receive paths
• Auto padding on transmits and stripping on receives
• Configured and monitored through a host interface
• Hardware-selectable Device Control Register (DCR) bus or generic host bus interface
• Configurable flow control through Ethernet MAC Control PAUSE frames;
symmetrically or asymmetrically enabled
• Configurable support for jumbo frames of any length
• Configurable receive address filter for unicast, multicast, and broadcast addresses
• Media Independent Interface (MII), Gigabit Media Independent Interface (GMII), and
Reduced Gigabit Media Independent Interface (RGMII)
• Includes a 1000BASE-X Physical Coding Sublayer (PCS) and a Physical Medium
Attachment (PMA) sublayer for use with the RocketIO™ Multi-Gigabit Transceiver
(MGT) to provide a complete on-chip 1000BASE-X implementation
• Serial Gigabit Media Independent Interface (SGMII) supported through MGT
interface to external copper PHY layer for full-duplex operation only
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