Xilinx Virtex-4 - Chapter 5: Miscellaneous Functions; Clock Frequency Support

Embedded Tri-Mode Ethernet MAC User Guide www.xilinx.com 147
UG074 (v2.2) February 22, 2010
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Chapter 5
Miscellaneous Functions
This chapter provides useful design information for the Virtex®-4 FPGA Embedded Tri-
Mode Ethernet MAC. It contains the following sections:
• “Clock Frequency Support”
• “Ethernet MAC Configuration,” page 149
• “Auto-Negotiation Interrupt,” page 151
Clock Frequency Support
Table 5-1 through Table 5-5 summarize the supported clock frequencies of the Ethernet
MAC. All clock signal output frequencies for both the transmit and receive modules are
generated in the clock-generation module of the Ethernet MAC.
Table 5-1: Transmit Clock Speeds (PHYEMAC#GTXCLK)
Clock Signals Direction 1000 Mb/s 100 Mb/s 10 Mb/s
PHYEMAC#GTXCLK Input 125 MHz 125 MHz 125 MHz
Table 5-2: Receive Clock Speeds (PHYEMAC#RXCLK)
Clock Signals Direction 1000 Mb/s 100 Mb/s 10 Mb/s
PHYEMAC#RXCLK Input 125 MHz 25 MHz 2.5 MHz
Table 5-3: Client Clock Frequency
Data Rate Direction 1000 Mb/s 100 Mb/s 10 Mb/s
EMAC#CLIENTRXCLIENTCLKOUT/
CLIENTEMAC#RXCLIENTCLKIN
Output/
Input
125 MHz 12.5 MHz 1.25 MHz
EMAC#CLIENTTXCLIENTCLKOUT/
CLIENTEMAC#TXCLIENTCLKIN
Output/
Input
125 MHz 12.5 MHz 1.25 MHz
Table 5-4: MII/GMII/RGMII Clock Frequency
Clock Signals Direction 1000 Mb/s 100 Mb/s 10 Mb/s
EMAC#CLIENTTXGMIIMIICLKOUT/
CLIENTEMAC#TXGMIIMIICLKIN
Output/
Input
125 MHz 25 MHz 2.5 MHz
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